Verilog分频器与数码管

暑期课又在做FPGA了。

每次都写一遍分频器真的挺费事的，所以干脆现在给它记下来。

分频器

---

可以用于奇分频和偶分频。

module mydivider(
	input clk,
	input reset,
	output dclk);
	
	parameter width = 3;
	parameter n = 5;
	
	reg dclk_p, dclk_n;
	
	reg [width-1:0] count_p = 0;
	reg [width-1:0] count_n = 0;
	
	always @ (posedge clk, negedge reset) begin
		if(~reset) begin
			count_p <= 0;
			dclk_p <= 0;
		end
		else begin
			count_p <= count_p + 1;
			case(count_p)
				n/2-1: dclk_p <= 0;
				n-1: begin
					dclk_p <= 1;
					count_p <= 0;
				end
				default: dclk_p <= dclk_p;
			endcase
		end
	end
	
	always @ (negedge clk, negedge reset) begin
		if(~reset) begin
			count_n <= 0;
			dclk_n <= 0;
		end
		else begin
			count_n <= count_n + 1;
			case(count_n)
				n/2-1: dclk_n <= 0;
				n-1: begin
					dclk_n <= 1;
					count_n <= 0;
				end
				default: dclk_n <= dclk_n;
			endcase
		end
	end
	
	assign dclk = n%2 == 1 ? dclk_p | dclk_n : dclk_p;
	
endmodule

数码管 共阳

---

没有点的数码管代码（问就是板子没连，我也不知道为啥…

记录这个纯属是不想再写一遍这些管子的的亮灭了。

16个case分别对应0 - F的显示。

module nixietube(
	input [3:0] data,
	output reg [6:0] show);
	
	always begin
		case(data[3:0])
			4'd0: show <= 7'b1000000;
			4'd1: show <= 7'b1111001;
			4'd2: show <= 7'b0100100;
			4'd3: show <= 7'b0110000;
			4'd4: show <= 7'b0011001;
			4'd5: show <= 7'b0010010;
			4'd6: show <= 7'b0000010;
			4'd7: show <= 7'b1111000;
			4'd8: show <= 7'b0000000;
			4'd9: show <= 7'b0010000;
			4'd10: show <= 7'b0001000;
			4'd11: show <= 7'b0000011;
			4'd12: show <= 7'b1000110;
			4'd13: show <= 7'b0100001;
			4'd14: show <= 7'b0000110;
			4'd15: show <= 7'b0001110;
			default: show <= 7'b1000000;
		endcase
	end

endmodule

「向着星辰与深渊」