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FPGA上的UART协议。

RX端的时钟是16×波特率；TX端则是等于波特率

本代码数据格式： 1 起始 8 数据 1 结束

RX端代码

---

clk - 时钟

rst - 重置 低有效

din - 接收信号线

srecv - 读取信号 上升沿触发

data - 接收数据

module uart_rx(
	input clk,
	input rst,
	input din,
	output reg srecv = 0,
	output reg [7:0] data = 0);
	
	reg [3:0] count = 0;
	reg [1:0] state = 0;
	reg [2:0] i = 0;
	
	always @ (posedge clk, negedge rst) begin
		if(~rst) begin
			count <= 0;
			i <= 0;
			srecv <= 0;
			data <= 0;
			state <= 2'h0;
		end
		else begin
			case(state)
				2'h0: begin
					if(din == 0)
						if(count != 15)
							count <= count + 1;
						else begin
							count <= 0;
							state <= 2'h1;
							srecv <= 0;
						end
					else
						count <= 0;
				end
				
				2'h1: begin
					if(count != 15) begin
						count <= count + 1;
						if(count == 10) begin
							data[i] <= din;
						end
					end
					else begin
						count <= 0;

						if(i == 7)
							state <= 2'h2;

						i <= i + 1;
					end
				end
				
				2'h2: begin
					if(count != 15)
						count <= count + 1;
					else begin
						count <= 0;
						state <= 2'h0;
						srecv <= 1;
					end
				end
				
			endcase
		end
	end
	
endmodule

TX端代码

---

clk - 时钟

rst - 重置 低有效

ssend - 发送信号 上升沿触发

data - 发送数据

send - 发送状态 高为正在发送

dout - 发送信号线

module uart_tx(
	input clk,
	input rst,
	input ssend,
	input [7:0] data,
	output reg send = 0,
	output reg dout = 1);
	
	reg [1:0] state = 2'h2;
	reg [7:0] sdata = 0;
	reg [3:0] i = 0;
	
	reg last_check = 0;
	reg check = 0;
	
	always @ (posedge ssend, negedge rst) begin
		if(~rst) begin
			sdata <= 0;
			check <= 0;
		end
		else begin
			sdata <= data;
			check <= ~check;
		end
	end
	
	always @ (posedge clk, negedge rst) begin
		if(~rst) begin
			i <= 0;
			dout = 1;
			state <= 2'h2;
			last_check = 0;
		end
		else begin
			if(check != last_check) begin
					state <= 2'h0;
					last_check = check;
			end
		
			case(state)
				2'h0: begin
					send <= 1;
					dout = 0;
					state <= 2'h1;
				end

				2'h1: begin
					dout = sdata[i];
					
					if(i != 7) begin
						i <= i + 1;
					end
					else begin
						i <= 0;
						state <= 2'h2;
					end
				end
					
				2'h2: begin
					dout = 1;
					send <= 0;
				end
					
			endcase
		end
	end
	
endmodule